FIG. 1 is a schematic diagram illustrating a conventional eight-bit input deserializer 100. In operation, input data is shifted through the first register bank 1021. When the first register bank 1021 is full, the input data is captured in parallel in the second register bank 1022. The least significant bit or the most significant bit of the input data is not necessarily captured at the top or bottom of the second register bank 1022, but could be captured in any of the eight flip flops of the second register bank 1022. Thus, a barrel shifter 104 comprising eight eight-to-one multiplexers is positioned between the second register bank 1022 and the third register bank 1023. The barrel shifter 104 allows any bit from the second register bank 1022 to be re-mapped to any input in the third register bank 1023. The output bits can therefore be re-ordered as necessary.
Although deserializers such as the deserializer 100 are effective in re-ordering the output bits, they are very difficult to scale. In particular, the faster the input data is, the wider the deserializer needs to be. However, the more bits that are in the register banks 102, the slower the overall circuit will be due to the larger muxing and the increased loading on each register output of the second register bank 1022. The only way to make the deserializer 100 operate at speed is to increase the drive strength and reduce the circuit delay by increasing the size of the circuitry. This makes the deserializer 100 impractical for use in small, low-cost integrated circuit (IC) devices such as small field programmable gate arrays (FPGAs).